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THE RISC-V READER : An Open Architecture Atlas
David Patterson ¤Ó µµ¼­ÃâÆÇ È«¸ª(È«¸ª°úÇÐÃâÆÇ»ç)
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181page/193*236*15
  • ISBN
9780999249116/0999249118
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  • Á¦ÈÞ¸ô ÁÖ¹® ½Ã °í°´º¸»ó, ÀϺΠÀ̺¥Æ® Âü¿© ¹× ÁõÁ¤Ç° ÁõÁ¤, ÇÏ·ç/´çÀÏ ¹è¼Û¿¡¼­ Á¦¿ÜµÇ¹Ç·Î Âü°í ¹Ù¶ø´Ï´Ù.
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  • RISC-V Reference Card List of Figures Preface 1 Why RISC-V? 2 RV321: RISC-V Base Integer ISA 3 RISC-V Assembly Language 4 RV23Ml Multiply and Divide 5 RV32FD: Single/Double Floating Point 6 RV32A: Atomic 7 RV32C: Compressed Instructions 8 RV32V: Vector 9 RV64: 64-BIT Address Instructions 10 RV32/64 Privileged Architectecture 11 Future RISC-V Optional Extensions
  • David Patterson [Àú]
  • David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1977.His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Prof. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Prof. Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH. ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry.
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